1. Field
Embodiments relate to buried channel array transistor (BCAT) devices and methods of forming BCAT devices. More particularly, embodiments relate to a BCAT device that has a shorter height and/or reduced loading capacitance than conventional devices.
2. Description of the Related Art
As semiconductor devices are becoming more and more integrated, device characteristics may suffer. For example, threshold voltages of devices, e.g., transistors, may be lowered. Refresh characteristics may also be degraded as channel lengths of transistors are shortened. Buried channels may be employed to help alleviate, e.g., such problems. More particularly, in a memory device, e.g., dynamic random access memory (DRAM) including BCATs, cell bit lines may be arranged above a substrate. Thus, e.g., a loading capacitance of the bit lines may be relatively high, a height of the bit line relative to the substrate may be high and/or an overall height of the DRAM as a result of, e.g., the bit lines may be tall.